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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9848/ad9849 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. ccd signal processors with integrated timing driver functional block diagram clamp dout ccdin pblk vrt vrb internal registers 2db to 36db sync generator sdata sck sl clpob 10 or 12 vga ad9848/ad9849 4 6db precision timing core adc vref clamp internal clocks pxga cds horizontal drivers 4 rg h1?4 hd vd cli clpdm features ad9848: 10-bit, 20 mhz version ad9849: 12-bit, 30 mhz version correlated double sampler (cds) ? db to +10 db pixel gain amplifier ( pxga ) 2 db to 36 db 10-bit variable gain amplifier (vga) 10-bit 20 mhz a/d converter (ad9848) 12-bit 30 mhz a/d converter (ad9849) black level clamp with variable level control complete on-chip timing driver precision timing core with 1 ns resolution @ 20 msps on-chip 3 v horizontal and rg drivers (ad9848) on-chip 5 v horizontal and rg drivers (ad9849) 48-lead lqfp package applications digital still cameras product description the ad9848 and ad9849 are highly integrated ccd signal pro- cessors for digital still camera applications. both include a complete analog front end with a/d conversion, combined with a program- mable timing driver. the precision timing core allows adjustment of high speed clocks with approximately 1 ns resolution. the ad9848 is specified at pixel rates of 20 mhz, and the ad9849 is specified at 30 mhz. the analog front end includes black level clamping, cds, pxga , vga, and a 10-bit or 12-bit a/d converter. the timing driver provides the high speed ccd clock drivers for rg and h1?4. operation is programmed using a 3- wire serial interface. packaged in a space saving 48-lead lqfp, the ad9848 and ad9849 are specified over an operating temperature range of ?0 c to +85 c. pxga is a registered trademark and precision timing is a trademark of analog devices, inc.
rev. a ? ad9848/ad9849 ?pecifications general specifications parameter min typ max unit temperature range operating ?0 +85 c storage ?5 +150 c maximum clock rate ad9848 20 mhz ad9849 30 mhz power supply voltage, ad9848 analog (avdd1, 2, 3) 2.7 3.6 v digital1 (dvdd1) h1?4 2.7 3.6 v digital2 (dvdd2) rg 2.7 3.6 v digital3 (dvdd3) d0?11 3.0 v digital4 (dvdd4) all other digital 3.0 v power supply voltage, ad9849 analog (avdd1, 2, 3) 2.7 3.6 v digital1 (dvdd1) h1?4 3.0 5.5 v digital2 (dvdd2) rg 3.0 5.5 v digital3 (dvdd3) d0?11 3.0 v digital4 (dvdd4) all other digital 3.0 v power dissipation, ad9848 20 mhz, dvdd1, 2 = 3 v, 100 pf h loading 220 mw total shutdown mode 1 mw power dissipation, ad9849 30 mhz, dvdd1, 2 = 5 v, 100 pf h loading 450 mw total shutdown mode 1 mw specifications subject to change without notice.
rev. a ? ad9848/ad9849 (t min to t max , avdd1 = dvdd3, dvdd4 = 2.7 v, dvdd1, dvdd2 = 2.7 v (ad9848), dvdd1, dvdd2 = 5.25 v (ad9849), c l = 20 pf, unless otherwise noted.) digital specifications parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v cli input high level input voltage (avdd1, 2 + 0.5 v) v ih?li 1.85 v low level input voltage v il?li 0.85 v rg and h-driver outputs, ad9848 high level output voltage (dvdd1, 2 ?0.5 v) v oh 2.2 v low level output voltage v ol 0.5 v maximum output current (programmable) 24 ma maximum load capacitance 100 pf rg and h-driver outputs, ad9849 high level output voltage (dvdd1, 2 ?0.5 v) v oh 4.75 v low level output voltage v ol 0.5 v maximum output current (programmable) 24 ma maximum load capacitance 100 pf specifications subject to change without notice.
rev. a ad9848/ad9849 ? ad9848?nalog specifications (t min to t max , avdd = dvdd = 3.0 v, f cli = 20 mhz, unless otherwise noted.) parameter min typ max unit notes cds gain 0 db allowable ccd reset transient * 500 mv see input waveform in note max input range before saturation * 1.0 v p-p max ccd black pixel amplitude * 150 mv pixel gain amplifier ( pxga ) max input range 1.0 v p-p max output range 1.6 v p-p gain control resolution 64 steps gain monotonicity guaranteed gain range min gain (32) ? db med gain (0) 4 db medium gain (4 db) is default setting max gain (31) 10 db variable gain amplifier (vga) max input range 1.6 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity guaranteed gain range low gain (91) 2 db max gain (1023) 36 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level (0) 0 lsb max clamp level (255) 63.75 lsb a/d converter resolution 10 bits differential nonlinearity (dnl) 0.4 1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (vrt) 2.0 v reference bottom voltage (vrb) 1.0 v system performance vga gain accuracy specifications include entire signal chain gain includes 4 db default pxga g ain low gain (91) 5 6 7 db max gain (1023) 38 39.5 41 db peak nonlinearity, 500 mv input signal 0.2 % 12 db gain applied total output noise 0.2 lsb rms ac grounded input, 6 db gain applied power supply rejection (psr) 40 db measured with step change on supply * input signal characteristics defined as follows: 500mv typ reset transient 150mv max optical black pixel 1v max input signal range specifications subject to change without notice.
rev. a ? ad9848/ad9849 ad9849?nalog specifications (t min to t max , avdd = dvdd = 3.0 v, f cli = 30 mhz, unless otherwise noted.) parameter min typ max unit notes cds gain 0 db allowable ccd reset transient * 500 mv see input waveform in note max input range before saturation * 1.0 v p-p max ccd black pixel amplitude * 150 mv pixel gain amplifier ( pxga ) max input range 1.0 v p-p max output range 1.6 v p-p gain control resolution 64 steps gain monotonicity guaranteed gain range min gain (32) ? db med gain (0) 4 db medium gain (4 db) is default setting max gain (31) 10 db variable gain amplifier (vga) max input range 1.6 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity guaranteed gain range low gain (91) 2 db max gain (1023) 36 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level (0) 0 lsb max clamp level (255) 255 lsb a/d converter resolution 12 bits differential nonlinearity (dnl) 0.5 1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (vrt) 2.0 v reference bottom voltage (vrb) 1.0 v system performance gain accuracy specifications include entire signal chain gain includes 4 db default pxga gain low gain (91) 5 6 7 db max gain (1023) 38 39.5 41 db peak nonlinearity, 500 mv input signal 0.2 % 12 db gain applied total output noise 0.6 lsb rms ac grounded input, 6 db gain applied power supply rejection (psr) 40 db measured with step change on supply * input signal characteristics defined as follows: 500mv typ reset transient 150mv max optical black pixel 1v max input signal range specifications subject to change without notice.
rev. a ? ad9848/ad9849 timing specifications (c l = 20 pf, f cli = 20 mhz (ad9848) or 30 mhz (ad9849), serial timing in figures 3a and 3b, unless otherwise noted.) parameter symbol min typ max unit master clock (cli), ad9848 cli clock period t cli 50 ns cli high/low pulsewidth t adc 25 ns delay from cli to internal pixel period position t clidly 6ns master clock (cli), ad9849 cli clock period t conv 33.33 ns cli high/low pulsewidth t adc 16.67 ns external mode clamping clpdm pulsewidth t cdm 410 pi xels clpob pulsewidth * t cob 220 pi xels sample clocks shp rising edge to shd rising edge (ad9848) t s1 20 ns shp rising edge to shd rising edge (ad9849) t s1 13 ns data outputs output delay from programmed edge t od 6ns pipeline delay 9 cycles serial interface maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns sck falling edge to sdata valid read t dv 10 ns * maximum clpob pulsewidth is for functional operation only. wider typical pulses are recommended to achieve low noise clamp refe rence. specifications subject to change without notice.
rev. a ad9848/ad9849 ? absolute maximum ratings with parameter respect to min max unit avdd1, 2, 3 avss ?.3 +3.9 v dvdd1, dvdd2 (ad9848) dvss ?.3 +3.9 v dvdd1, dvdd2 (ad9849) dvss ?.3 +5.5 v dvdd3, 4 dvss ?.3 +3.9 v digital outputs dvss3 ?.3 dvdd3 + 0.3 v clpob, clpdm, blk dvss4 ?.3 dvdd4 + 0.3 v cli avss ?.3 avdd + 0.3 v sck, sl, sdata dvss4 ?.3 dvdd4 + 0.3 v vrt, vrb avss ?.3 avdd + 0.3 v byp1?, ccdin avss ?.3 avdd + 0.3 v junction temperature 150 c lead temperature (10 sec) 300 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9848/ad9849 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device thermal characteristics thermal resistance 48-lead lqfp package ja = 92 c ordering guide temperature package package model range description option ad9848akst ?0 c to +85 ct hin plastic quad st-48 flatpack (lqfp) AD9849AKST ?0 c to +85 ct hin plastic quad st-48 flatpack (lqfp)
rev. a ad9848/ad9849 ? 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) sl reft refb cmlevel avss3 avdd3 ccdin ( lsb) d0 d1 d2 d3 d4 nc = no connect dvss3 dvdd3 d5 d6 byp2 avdd2 ad9848 d7 avss2 nc nc dvdd4 dvss4 hd vd pblk hblk clpdm clpob sck sdi h1 h2 dvss1 dvdd1 h3 h4 dvss2 rg dvdd2 avss1 cli avdd1 d8 ( msb) d9 byp1 byp3 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) sl reft refb cmlevel avss3 avdd3 ccdin d2 d3 d4 dvss3 dvdd3 d5 d6 byp2 avdd2 ad9849 d7 avss2 d1 d0 (lsb) dvdd4 dvss4 hd vd pblk hblk clpdm clpob sck sdi h1 h2 dvss1 dvdd1 h3 h4 dvss2 rg dvdd2 avss1 cli avdd1 d8 ( msb) d11 byp1 byp3 d9 d10 pin function descriptions pin mnemonic type * description 1? d0?4 do data outputs ad9848 only 1? d2?6 do data outputs ad9849 only 6 dvss3 p digital ground 3 ?data outputs 7 dvdd3 p digital supply 3 ?data outputs 8?2 d5?9 do data outputs (d9 is msb) ad9848 only 8?2 d7?11 do data outputs (d9 is msb) ad9849 only 13, 14 h1, h2 do horizontal clocks (to ccd) 15 dvss1 p digital ground 1 ?h drivers 16 dvdd1 p digital supply 1 ?h drivers 17, 18 h3, h4 do horizontal clocks (to ccd) 19 dvss2 p digital ground 1 ?rg driver 20 rg do reset gate clock (to ccd) 21 dvdd2 p digital supply 2 ?rg driver 22 avss1 p analog ground 1 23 cli di master clock input 24 avdd1 p analog supply 1 25 avss2 p analog ground 2 26 avdd2 p analog supply 2 27 byp1 ao bypass pin (0.1 f to avss) 28 byp2 ao bypass pin (0.1 f to avss) 29 ccdin ai analog input for ccd signal 30 byp3 ao bypass pin (0.1 f to avss) 31 avdd3 p analog supply 3 32 avss3 p analog ground 3 33 cmlevel ao internal bias level decoupling (0.1 f to avss) 34 refb ao reference bottom decoupling (1.0 f to avss) 35 reft ao reference top decoupling (1.0 f to avss) 36 sl di 3-wire serial load (from p) 37 sdi di 3-wire serial data input (from p) 38 sck di 3-wire serial clock (from p) 39 clpob di optical black clamp pulse 40 clpdm di dummy black clamp pulse 41 hblk di hclk blanking pulse 42 pblk di preblanking pulse 43 vd di vertical sync pulse 44 hd di horizontal sync pulse 45 dvss4 p digital ground 4 ?vd, hd, clpob, clpdm, hblk, pblk, sck, sl, sdata 46 dvdd4 p digital supply 4 ?vd, hd, clpob, clpdm, hblk, pblk, ck, sl, sdata 47, 48 nc nc internally not connected ad9848 only 47, 48 d0, d1 do data output (d0 is lsb) ad9849 only * type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power pin configuration
rev. a ? ad9848/ad9849 equivalent input/output circuits r avdd2 avss2 avss2 circuit 1. ccdin (pin 29) avdd1 avss1 330 cli 25k 1.4v circuit 2. cli (pin 23) dvdd4 dvdd3 dvss4 dvss3 data three- state dout circuit 3. data outputs d0?11 (pins 1?, 8?2, 47?8) dvdd4 dvss4 330 circuit 4. digital inputs (pins 36?4) dvdd1 dvss1 data enable output circuit 5. h1?4 and rg (pins 13, 14, 17, 18, 20)
rev. a ad9848/ad9849 ?0 ?ypical performance characteristics ?.50 0 1000 400 200 600 800 ?.25 0 0.25 0.50 tpc 1. ad9848 typical dnl vga gain code ?lsb 0 0 1000 400 output noise ?lsb 200 1 600 800 2 3 4 tpc 2. ad9848 output noise vs. vga gain setting 0 1000 500 1500 2000 2500 3000 3500 4000 0 ?.5 0.5 ?.25 0.25 tpc 3. ad9849 typical dnl vga gain code ?lsb 15 0 0 1000 400 output noise ?lsb 200 5 600 10 800 tpc 4. ad9849 output noise vs. vga gain setting
rev. a ad9848/ad9849 ?1 system overview ccd serial interface dout hd, vd cli digital image processing asic v-driver v1?4, vsg1?sg8, subck h1?4, rg ccdin ad9848/ad9849 integrated afe+td figure 1a. typical application (internal mode) ccd serial interface dout hd, vd cli pblk hblk clpdm clpob digital image processing asic v-driver v1?4, vsg1?sg8, subck h1?4, rg ccdin ad9848/ad9849 integrated afe+td figure 1b. typical application (external mode) figures 1a and 1b show the typical system application diagrams for the ad9848/ad9849. the ccd output is processed by the ad9848/ad9849? afe circuitry, which consists of a cds, pxga , vga, black level clamp, and a/d converter. the digitized pixel information is sent to the digital image processor chip, where all post-processing and compression occurs. to operate the ccd, ccd timing parameters are programmed into the ad9848/ad9849 from the image processor, through the 3-wire serial interface. from the system master clock, cli, provided by the image processor, the ad9848/ad9849 generates the high speed ccd clocks and all internal afe clocks. all ad9848/ad9849 clocks are synchronized with vd and hd. figure 1a shows the ad9848/ad9849 used in internal mode, in which all the horizontal pulses (clpob, clpdm, pblk, and hblk) are programmed and generated internally. fig ure 1b shows the ad9848/ad9849 operating in external mode, in which the horizontal pulses are supplied externally by the image processor. the h-drivers for h1?4 and rg are included in the ad9848/ a d9849, allowing these clocks to be directly connected to the ccd. h-drive voltage of 5 v is supported in the ad9849. figure 2 shows the horizontal and vertical counter dimensions for the ad9848/ad9849. all internal horizontal clocking is programmed using these dimensions to specify line and pixel locations. maximum field dimensions 12-bit horizontal = 4096 pixels max 12-bit vertical = 4096 lines max figure 2. vertical and horizontal counters
rev. a ad9848/ad9849 ?2 serial interface timing sdata a0 a1 a2 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 xx xx sck sl a3 notes 1. sdata bits are latched on sck rising edges. 2. 14 sck edges are needed to write address and data bits. 3. for 16-bit systems, two extra dummy bits may be written. dummy bits are ignored. 4. new data is updated at either the sl rising edge, or at the hd falling edge after the next vd falling edge. 5. vd/hd update position may be delayed to any hd falling edge in the field using the update register. vd hd sl updated vd/hd updated t ds t dh t ls t lh figure 3a. serial write operation sdata a0 a1 a2 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 sck sl a3 notes 1. multiple sequential registers may be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 6-bit data-words. 3. the address will automatically increment with each 6-bit data-word (all 6 bits must be written). 4. sl is held low until the last desired register has been loaded. 5. new data is updated at either the sl rising edge, or at the hd falling edge after the next vd falling edge. d0 d1 d2 d3 d4 d5 d0 ... ... ... data for starting register address data for next register address d2 d1 figure 3b. continuous serial write operation complete register listing table i. register description register description oprmode afe operation modes h1drv h1 drive current ctlmode afe control modes h2drv h2 drive current preventpdate prevents loading of vd-updated registers h3drv h3 drive current readback enables serial register readback mode h4drv h4 drive current vdhdpol vd/hd active polarity rgpol rg polarity fieldval internal field pulse value rgposloc rg positive edge location hblkretime retimes the h1 hblk to internal clock rgnegloc rg negative edge location tgcore_rstb reset bar signal for internal tg core rgdrv rg drive current h12pol h1/h2 polarity control shpposloc shp sample location h1posloc h1 positive edge location shdposloc shd sample location h1negloc h1 negative edge location notes 1. all addresses and default values are expressed in hexadecimal. 2. all registers are vd/hd updated as shown in figure 3a, except for the above-listed registers that are sl updated.
rev. a ad9848/ad9849 ?3 bit default address content width value register name register description afe registers # bits 56 00 [5:0] 6 00 oprmode[5:0] afe operation m ode (see afe register breakdown) 01 [1:0] 2 00 oprmode[7:6] 02 [5:0] 6 16 ccdgain[5:0] vga gain 03 [3:0] 4 02 ccdgain[9:6] 04 [5:0] 6 00 refblack[5:0] black clamp level 05 [1:0] 2 02 refblack[7:6] 06 [5:0] 6 00 ctlmode control mode (see afe register breakdown) 07 [5:0] 6 00 pxga gain0 pxga color 0 gain 08 [5:0] 6 00 pxga gain1 pxga color 1 gain 09 [5:0] 6 00 pxga gain2 pxga color 2 gain 0a [5:0] 6 00 pxga gain3 pxga color 3 gain miscellaneous/extra # bits 26 0f [5:0] 6 00 initial2 see recommended power-up sequence section. should be set to ??decimal (000100). 16 [0] 1 00 out_cont output control (0 = make all outputs dc inactive) 17 [5:0] 6 00 update[5:0] serial data update control. sets the line within the field 18 [5:0] 6 00 update[11:6] for serial data update to occur. 19 [0] 1 00 preventupdate prevent the update of the ?d/hd updated?registers 1b [5:0] 6 00 doutphase dout phase control 1c [0] 1 00 disablerestore disable ccdin dc restore circuit during pblk (1 = disable) 1d [0] 1 00 vdhdpol vd/hd active polarity (0 = low active, 1 = high active) 1e [0] 1 01 fieldval internal field pulse value (0 = next field odd, 1 = next field even) 1f [0] 1 00 hblkretime re-sync hblk to h1 clock 20 [5:0] 6 00 initial1 see reco mmended power-up sequence section. should be s et to ?3 decimal (110101). 26 [0] 1 00 tgcore_rstb tg core reset_bar (0 = hold tg core in reset, 1 = resume normal operation) accessing a double-wide register there are many double-wide registers in the ad9848/ad9849, for example, oprmode, clpdmtog1_0, and clpdmscp3, and so on. these registers are configured into two consecutive 6-bit registers with the least significant six bits located in the lower of the two addresses and the remaining most significant bits located in the higher of the two addresses. for example, the six lsbs of the clpdmscp3 register, clpdmscp3[5:0], are located at address 0x81. the most significant six bits of the clpdmscp3 register, clpdmscp3[11:6], are located at address 0x82. the following rules must be followed when accessing double- wide registers: 1. when accessing a double-wide register, both addresses must be written to. 2. the lower of the two consecutive addresses for the double- wide register must be written to first. in the example of the clpdmscp3 register, the contents of address 0x81 must be written first fol lowed by the contents of address 0x82. the register will be upd ated after the completion of the write to register 0x82, either at the next sl rising edge or next vd/hd falling edge. 3. a single write to the lower of the two consecutive ad- dresses of a double-wide register that is not followed by a write to the higher address of the registers is not per- mitted. this will not update the register. 4. a single write to the higher of the two consecutive ad- dresses of a double-wide register that is not preceded by a write to the lower of the two addresses is not permit- ted. although the write to the higher address will update the full double-wide register, the lower six bits of the register will be written with an indeterminate value if the lower address was not written first.
rev. a ad9848/ad9849 ?4 bit default address content width value register name register description clpdm # bits 146 64 [0] 1 01 clpdmdir clpdm internal/external (0 = internal, 1 = external) 65 [0] 1 00 clpdmpol clpdm external active polarity (0 = low active, 1 = high active) 66 [0] 1 01 clpdmspol0 sequence #0: start polarity for clpdm 67 [5:0] 6 2c clpdmtog1_0[5:0] sequence #0: toggle position 1 for clpdm 68 [5:0] 6 00 clpdmtog1_0[11:6] 69 [5:0] 6 35 clpdmtog2_0[5:0] sequence #0: toggle position 2 for clpdm 6a [5:0] 6 00 clpdmtog2_0[11:6] 6b [0] 1 01 clpdmspol1 sequence #1: start polarity for clpdm 6c [5:0] 6 3e clpdmtog1_1[5:0] sequence #1: toggle position 1 for clpdm 6d [5:0] 6 02 clpdmtog1_1[11:6] 6e [5:0] 6 16 clpdmtog2_1[5:0] sequence #1: toggle position 2 for clpdm 6f [5:0] 6 03 clpdmtog2_1[11:6] 70 [0] 1 00 clpdmspol2 sequence #2: start polarity for clpdm 71 [5:0] 6 3f clpdmtog1_2[5:0] sequence #2: toggle position 1 for clpdm 72 [5:0] 6 3f clpdmtog1_2[11:6] 73 [5:0] 6 3f clpdmtog2_2[5:0] sequence #2: toggle position 2 for clpdm 74 [5:0] 6 3f clpdmtog2_2[11:6] 75 [0] 1 01 clpdmspol3 sequence #3: start polarity for clpdm 76 [5:0] 6 3f clpdmtog1_3[5:0] sequence #3: toggle position 1 for clpdm 77 [5:0] 6 3f clpdmtog1_3[11:6] 78 [5:0] 6 3f clpdmtog2_3[5:0] sequence #3: toggle position 2 for clpdm 79 [5:0] 6 3f clpdmtog2_3[11:6] 00 0 clpdmscp0 clpdm sequence-change-position #0 (hardcoded to 0) 7a [1:0] 2 00 clpdmsptr0 clpdm sequence pointer for scp #0 7b [5:0] 6 3f clpdmscp1[5:0] clpdm sequence-change-position #1 7c [5:0] 6 3f clpdmscp1[11:6] 7d [1:0] 2 00 clpdmsptr1 clpdm sequence pointer for scp #1 7e [5:0] 6 3f clpdmscp2[5:0] clpdm sequence-change-position #2 7f [5:0] 6 3f clpdmscp2[11:6] 80 [1:0] 2 00 clpdmsptr2 clpdm sequence pointer for scp #2 81 [5:0] 6 3f clpdmscp3[5:0] clpdm sequence-change-position #3 82 [5:0] 6 3f clpdmscp3[11:6] 83 [1:0] 2 00 clpdmsptr3 clpdm sequence pointer for scp #3
rev. a ad9848/ad9849 ?5 bit default address content width value register name register description clpob # bits 146 84 [0] 1 01 clpobdir clpob internal/external (0 = internal, 1 = external) 85 [0] 1 00 clpobpol clpob external active polarity (0 = low active, 1 = high active) 86 [0] 1 01 clpobpol0 sequence #0: start polarity for clpob 87 [5:0] 6 0e clpobtog1_0[5:0] sequence #0: toggle position 1 for clpob 88 [5:0] 6 00 clpobtog1_0[11:6] 89 [5:0] 6 2b clpobtog2_0[5:0] sequence #0: toggle position 2 for clpob 8a [5:0] 6 00 clpobtog2_0[11:6] 8b [0] 1 01 clpobpol1 sequence #1: start polarity for clpob 8c [5:0] 6 2b clpobtog1_1[5:0] sequence #1: toggle position 1 for clpob 8d [5:0] 6 06 clpobtog1_1[11:6] 8e [5:0] 6 3f clpobtog2_1[5:0] sequence #1: toggle position 2 for clpob 8f [5:0] 6 3f clpobtog2_1[11:6] 90 [0] 1 00 clpobspol2 sequence #2: start polarity for clpob 91 [5:0] 6 3f clpobtog1_2[5:0] sequence #2: toggle position 1 for clpob 92 [5:0] 6 3f clpobtog1_2[11:6] 93 [5:0] 6 3f clpobtog2_2[5:0] sequence #2: toggle position 2 for clpob 94 [5:0] 6 3f clpobtog2_2[11:6] 95 [0] 1 01 clpobspol3 sequence #3: start polarity for clpob 96 [5:0] 6 3f clpobtog1_3[5:0] sequence #3: toggle position 1 for clpob 97 [5:0] 6 3f clpobtog1_3[11:6] 98 [5:0] 6 3f clpobtog2_3[5:0] sequence #3: toggle position 2 for clpob 99 [5:0] 6 3f clpobtog2_3[11:6] 00 0c lpobscp0 clpob sequence-change-position #0 (hardcoded to 0) 9a [1:0] 2 03 clpobsptr0 clpob sequence pointer for scp #0 9b [5:0] 6 01 clpobscp1[5:0] clpob sequence-change-position #1 9c [5:0] 6 00 clpobscp1[11:6] 9d [1:0] 2 01 clpobsptr1 clpob sequence pointer for scp #1 9e [5:0] 6 02 clpobscp2[5:0] clpob sequence-change-position #2 9f [5:0] 6 00 clpobscp2[11:6] a0 [1:0] 2 00 clpobsptr2 clpob sequence pointer for scp #2 a1 [5:0] 6 37 clpobscp3[5:0] clpob sequence-change-position #3 a2 [5:0] 6 03 clpobscp3[11:6] a3 [1:0] 2 03 clpobsptr3 clpob sequence pointer for scp #3
rev. a ad9848/ad9849 ?6 bit default address content width value register name register description hblk # bits 147 a4 [0] 1 01 hblkdir hblk internal/external (0 = internal, 1 = external) a5 [0] 1 00 hblkpol hblk external active polarity (0 = low active, 1 = high active) a6 [0] 1 01 hblkextmask hblk external masking polarity (0 = mask h1 and h3 low, 1 = mask h1 and h3 high) a7 [0] 1 01 hblkmask0 sequence #0: masking polarity for hblk a8 [5:0] 6 3e hblktog1_0[5:0] sequence #0: toggle low position for hblk a9 [5:0] 6 00 hblktog1_0[11:6] aa [5:0] 6 0d hblkbtog2_0[5:0] sequence #0: toggle high position for hblk ab [5:0] 6 06 hblkbtog2_0[11:6] ac [0] 1 01 hblkmask1 sequence #1: masking polarity for hblk ad [5:0] 6 38 hblktog1_1[5:0] sequence #1: toggle low position for hblk ae [5:0] 6 00 hblktog1_1[11:6] af [5:0] 6 3c hblktog2_1[5:0] sequence #1: toggle high position for hblk b0 [5:0] 6 02 hblktog2_1[11:6] b1 [0] 1 00 hblkmask2 sequence #2: masking polarity for hblk b2 [5:0] 6 3f hblktog1_2[5:0] sequence #2: toggle low position for hblk b3 [5:0] 6 3f hblktog1_2[11:6] b4 [5:0] 6 3f hblktog2_2[5:0] sequence #2: toggle high position for hblk b5 [5:0] 6 3f hblktog2_2[11:6] b6 [0] 1 01 hblkmask3 sequence #3: masking polarity for hblk b7 [5:0] 6 3f hblktog1_3[5:0] sequence #3: toggle low position for hblk b8 [5:0] 6 3f hblktog1_3[11:6] b9 [5:0] 6 3f hblktog2_3[5:0] sequence #3: toggle high position for hblk ba [5:0] 6 3f hblktog2_3[11:6] 00 0 hblkscp0 hblk sequence-change-position #0 (hardcoded to 0) bb [1:0] 2 00 hblksptr0 hblk sequence pointer for scp #0 bc [5:0] 6 3f hblkscp1[5:0] hblk sequence-change-position #1 bd [5:0] 6 3f hblkscp1[11:6] be [1:0] 2 00 hblksptr1 hblk sequence pointer for scp #1 bf [5:0] 6 3f hblkscp2[5:0] hblk sequence-change-position #2 c0 [5:0] 6 3f hblkscp2[11:6] c1 [1:0] 2 00 hblksptr2 hblk sequence pointer for scp #2 c2 [5:0] 6 3f hblkscp3[5:0] hblk sequence-change-position #3 c3 [5:0] 6 3f hblkscp3[11:6] c4 [1:0] 2 00 hblksptr3 hblk sequence pointer for scp #3
rev. a ad9848/ad9849 ?7 bit default address content width value register name register description pblk # bits 146 c5 [0] 1 01 pblkdir pblk internal/external (0 = internal, 1 = external) c6 [0] 1 00 pblkpol pblk external active polarity (0 = low active, 1 = high active) c7 [0] 1 01 pblkspol0 sequence #0: start polarity for pblk c8 [5:0] 6 3d pblktog1_0[5:0] sequence #0: toggle position 1 for pblk c9 [5:0] 6 00 pblktog1_0[11:6] ca [5:0] 6 2a pblkbtog2_0[5:0] sequence #0: toggle position 2 for pblk cb [5:0] 6 06 pblkbtog2_0[11:6] cc [0] 1 00 pblkspol1 sequence #1: start polarity for pblk cd [5:0] 6 2a pblktog1_1[5:0] sequence #1: toggle position 1 for pblk ce [5:0] 6 06 pblktog1_1[11:6] cf [5:0] 6 3f pblktog2_1[5:0] sequence #1: toggle position 2 for pblk d0 [5:0] 6 3f pblktog2_1[11:6] d1 [0] 1 00 pblkspol2 sequence #2: start polarity for pblk d2 [5:0] 6 3f pblktog1_2[5:0] sequence #2: toggle position 1 for pblk d3 [5:0] 6 3f pblktog1_2[11:6] d4 [5:0] 6 3f pblktog2_2[5:0] sequence #2: toggle position 2 for pblk d5 [5:0] 6 3f pblktog2_2[11:6] d6 [0] 1 01 pblkspol3 sequence #3: start polarity for pblk d7 [5:0] 6 3f pblktog1_3[5:0] sequence #3: toggle position 1 for pblk d8 [5:0] 6 3f pblktog1_3[11:6] d9 [5:0] 6 3f pblktog2_3[5:0] sequence #3: toggle position 2 for pblk da [5:0] 6 3f pblktog2_3[11:6] 00 0 pblkscp0 pblk sequence-change-position #0 (hardcoded to 0) db [1:0] 2 02 pblksptr0 pblk sequence pointer for scp #0 dc [5:0] 6 01 pblkscp1[5:0] pblk sequence-change-position #1 dd [5:0] 6 00 pblkscp1[11:6] de [1:0] 2 01 pblksptr1 pblk sequence pointer for scp #1 df [5:0] 6 02 pblkscp2[5:0] pblk sequence-change-position #2 e0 [5:0] 6 00 pblkscp2[11:6] e1 [1:0] 2 00 pblksptr2 pblk sequence pointer for scp #2 e2 [5:0] 6 37 pblkscp3[5:0] pblk sequence-change-position #3 e3 [5:0] 6 03 pblkscp3[11:6] e4 [1:0] 2 02 pblksptr3 pblk sequence pointer for scp #3 h1?4, rg, shp, shd # bits 53 e5 [0] 1 00 h1pol h1/h2 polarity control (0 = no inversion, 1 = inversion) e6 [5:0] 6 00 h1posloc h1 positive edge location e7 [5:0] 6 20 h1negloc h1 negative edge location e8 [2:0] 3 03 h1drv h1 drive strength (0 = off, 1 = 3.5 ma, 2 = 7 ma, 3 = 10.5 ma, 4 = 14 ma, 5 = 17.5 ma, 6 = 21 ma, 7 = 24.5 ma) e9 [2:0] 3 03 h2drv h2 drive strength ea [2:0] 3 03 h3drv h3 drive strength eb [2:0] 3 03 h4drv h4 drive strength ec [0] 1 00 rgpol rg polarity control (0 = no inversion, 1 = inversion) ed [5:0] 6 00 rgposloc rg positive edge location ee [5:0] 6 10 rgnegloc rg negative edge location ef [2:0] 3 02 rgdrv rg drive strength (0 = off, 1 = 3.5 ma, 2 = 7 ma, 3 = 10.5 ma, 4 = 14 ma, 5 = 17.5 ma, 6 = 21 ma, 7 = 24.5 ma) f0 [5:0] 6 24 shpposloc shp (positive) edge sampling location f1 [5:0] 6 00 shdposloc shd (positive) edge sampling location
rev. a ad9848/ad9849 ?8 bit default address content width value register name register description afe register breakdown serial address: oprmode [7:0] 8'h0 8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]} [1:0] 2'h0 powerdown[1:0] full power 2'h1 fast recovery 2'h2 reference standby 2'h3 total shutdown [2] disblack disable black loop clamping (high active) [3] test mode test mode?hould be set low [4] test mode test mode?hould be set high [5] test mode test mode?hould be set low [6] test mode test mode?hould be set low [7] test mode test mode?hould be set low ctlmode [5:0] 6'h0 serial address: 8'h06 {cltmode[5:0]} [2:0] 3'h0 ctlmode[2:0] off 3'h1 mosaic separate 3'h2 vd selected/mosaic interlaced 3'h3 mosaic repeat 3'h4 three-color 3'h5 three-color ii 3'h6 four-color 3'h7 four-color ii [3] enablepxga enable pxga (high active) [4] 1'h0 outputlat latch output data on selected dout edge 1'h1 leave output latch transparent [5] 1'h0 tristateout adc outputs are driven 1'h1 adc outputs are three-stated precision timing high speed timing generation the ad9848 and ad9849 generate flexible high speed timing signals using the precision timing core. this core is the founda- tion for generating the timing used for both the ccd and the afe; the reset gate rg, horizontal drivers h1?4, and the shp/shd sample clocks. a unique architecture makes it rou- tine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe correlated double sampling. timing resolution the precision timing core uses a 1 master clock input (cli) as a reference. this clock should be the same as the ccd pixel clock frequency. figure 4 illustrates how the internal timing core divides the master clock period into 48 steps or edge posi- tions. therefore, the edge resolution of the precision timing core is (t cli /48). for more information on using the cli input, see the driving the cli input section. high speed clock programmability figure 5 shows how the high speed clocks rg, h1?4, shp, and shd are generated. the rg pulse has programmable rising and falling edges and may be inverted using the polarity control. the horizontal clocks h1 and h3 have programmable rising and falling edges and polarity control. the h2 and h4 clocks are always inverses of h1 and h3, respectively. table ii summarizes the high speed timing registers and their parameters. the edge location registers are six bits wide, but there are only 48 valid edge locations available. therefore, the register values are mapped into four quadrants, with each quadrant containing 12 edg e locations. table iii shows the correct register values for the corresponding edge locations. figure 6 shows the range and default locations of the high speed clock signals.
rev. a ad9848/ad9849 ?9 notes 1. pixel clock period is divided into 48 positions, providing fine edge resolution for high speed clocks. 2. there is a fixed delay from the cli input to the internal pixel period positions ( t clidly = 6 ns typ). p[0] p[48] = p[0] p[12] p[24] p[36] 1 pixel period ... ... cli t clidly position figure 4. high speed clock resolution from cli master clock input h1/h3 h2/h4 ccd signal rg (1) (2) (3) (4) (5) (6) notes programmable clock positions: (1) rg rising edge and (2) falling edge (3) shp and (4) shd sample location (5) h1/h3 rising edge position and (6) falling edge position (h2/h4 are inverse of h1/h3) figure 5. high speed clock programmable locations p[0] pixel period rg h1/h3 rgf[12] p[48] = p[0] hf[24] shp[28] ccd signal p[24] p[12] p[36] hr[0] rgr[0] shd[48] notes 1. all signal edges are fully programmable to any of the 48 positions within one pixel period. 2. default positions for each signal are shown above. position t s1 figure 6. high speed clock default and programmable locations
rev. a ad9848/ad9849 ?0 h-driver and rg outputs in addition to the programmable timing positions, the ad9848/ a d9849 features on-chip output drivers for the rg and h1?4 outputs. these drivers are powerful enough to directly drive the ccd inputs. the h-driver current can be adjusted for optimum rise/fall time into a particular load by using the drv registers. the rg drive current is adjustable using the rgdrv register. each 3-bit drv register is adjustable in 3.5 ma increments, with the minimum setting of 0 equal to off or three-state, and the maximum setting of 7 equal to 24.5 ma. as shown in figure 7, the h2/h4 outputs are inverses of h1/h3. the internal propagation delay resulting from the signal inversion is less than l ns, which is significantly less than the typical rise time driving the ccd load. this results in a h1/h2 crossover voltage at approximately 50% of the output swing. the crossover voltage is not programmable. digital data outputs the ad9848/ad9849 data output phase is programmable using the doutphase register. any edge from 0 to 47 may be programmed, as shown in figure 8. horizontal clamping and blanking the ad9848/ad9849? horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. as with the vertical timing generation, individual sequences are defined for each signal and are then organized into multiple regions during image readout. this allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts. table ii. h1?4, rg, shp, shd timing parameters register name length range description pol 1b high/low polarity control for h1, h3, and rg (0 = no inversion, 1 = inversion) posloc 6b 0?7 edge location positive edge location for h1, h3, and rg sample location for shp, shd negloc 6b 0?7 edge location negative edge location for h1, h3, and rg drv 3b 0? current steps drive current for h1?4 and rg outputs (3.5 ma per step) table iii. precision timing edge locations quadrant edge location (decimal) register value (decimal) register value (binary) i0 to 11 0 to 11 000000 to 001011 ii 12 to 23 16 to 27 010000 to 011011 iii 24 to 35 32 to 43 100000 to 101011 iv 36 to 47 48 to 59 110000 to 111011 fixed crossover voltage h1/h3 h2/h4 t pd h2/h4 h1/h3 t rise t pd t rise << figure 7. h-clock inverse phase relationship notes 1. digital output data (dout) phase is adjustable with respect to the pixel period. 2. within 1 clock period, the data transition can be programmed to any of the 48 locations. p[0] p[48] = p[0] cli 1 pixel period p[12] p[24] p[36] dout t od figure 8. digital output phase adjustment
rev. a ?1 ad9848/ad9849 h2 = h4 = high during the blanking, as shown in figure 11. up to four individual sequences are available for hblk. horizontal sequence control the ad9848/ad9849 uses sequence change positions (scp) and sequence pointers (sptr) to organize the individual horizontal sequences. up to four scps are available to divide the readout into four separate regions, as shown in figure 12. the scp 0 is always hard-coded to line 0, and scp1? are register programmable. during each region bounded by the scp, the sptr registers designate which sequence is used by each signal. clpob, clpdm, pblk, and hblk each have a separate set of scp. for example, clpobscp1 will define region 0 for clpob, and in that region any of the four individual clpob sequences may be selected with the clpobsptr registers. the next scp defines a new region and in that region each signal can be assigned to a different individual sequence. the sequence control registers are summarized in table vi. (3) (2) (1) hd clpob clpdm pblk . . . notes programmable settings: (1) start polarity (clamp and blank region are active low) (2) first toggle position (3) second toggle position . . . clamp clamp figure 9. clamp and preblank pulse placement (2) (1) hd hblk . . . notes programmable settings: (1) first toggle position = start of blanking (2) second toggle position = end of blanking . . . blank blank figure 10. horizontal blanking (hblk) pulse placement hd hblk . . . the polarity of h1 during blanking is programmable (h2 is opposite polarity of h1) . . . h1/h3 h1/h3 h2/h4 . . . . . . figure 11. hblk masking control individual clpob, clpdm, pblk sequences the afe horizontal timing consists of clpob, clpdm, and pblk, as shown in figure 9. these three signals are indepen- dently programmed using the registers in table iv. spol is the start polarity for the signal, and tog1 and tog2 are the first and second toggle positions of the pulse. all three signals are active low and should be programmed accordingly. up to four individual sequences can be created for each signal. individual hblk sequences the hblk programmable timing shown in figure 10 is similar to clpob, clpdm, and pblk. however, there is no start polar- ity control. only the toggle positions are used to designate the start and the stop positions of the blanking period. additionally, there is a polarity control hblkmask that designates the polarity of the horizontal clock signals h1?4 during the blank- ing period. setting hblkmask high will set h1 = h3 = low and
rev. a ad9848/ad9849 ?2 up to four individual horizontal clamp and blanking regions may be programmed within a single field, using the sequence change positions. sequence change of position #1 sequence change of position #2 sequence change of position #3 single field (1 vd interval) clamp and pblk sequence region 0 sequence change of position #0 (v-counter = 0) clamp and pblk sequence region 3 clamp and pblk sequence region 2 clamp and pblk sequence region 1 figure 12. clamp and blanking sequence flexibility table iv. clpob, clpdm, pblk individual sequence parameters register name length range description spol 1b high/low starting polarity of clamp and blanking pulses for sequences 0? tog1 12b 0?095 pixel location first toggle position within the line for sequences 0? tog2 12b 0?095 pixel location second toggle position within the line for sequences 0? table v. hblk individual sequence parameters register name length range description hblkmask 1b high/low masking polarity for h1 for sequences 0? (0 = h1 low, 1 = h1 high) hblktog1 12b 0?095 pixel location first toggle position within the line for sequences 0? hblktog2 12b 0?095 pixel location second toggle position within the line for sequences 0? table vi. horizontal sequence control parameters for clpob, clpdm, pblk, and hblk register name length range description scp1?cp3 12b 0?095 line number clamp/blank scp to define horizontal regions 0? sptr0?ptr3 2b 0? sequence number sequence pointer for horizontal regions 0? h-counter synchronization the h-counter reset occurs on the sixth cli rising edge following the hd falling edge. the pxga steering is synchronized with the reset of the internal h-counter (see figure 13). 000 1 12 111 0 03 11 00 012345678910111214150123 023 4 h-counter reset vd notes 1. internal h-counter is reset on the sixth cli rising edge following the hd falling edge. 2. pxga steering is syncronized with the reset of the internal h-counter (mosaic separate mode is shown). 3. vd falling edge should occur one clock cycle before hd falling edge for proper pxga line synchronization. hd xx xxx x x pxga gain register cli xx xxx x x h-counter (pixel counter) 3ns min 23 5 3ns min x x figure 13. h-counter synchronization
rev. a ad9848/ad9849 ?3 recommended power-up sequence when the ad9848 and ad9849 are powered up, the following sequence is recommended (refer to figure 14 for each step). 1. turn on power supplies for ad9848/ad9849. 2. apply the master clock input cli, vd, and hd. 3. the precision timing core must be reset by writing a ??to the tgcore_rstb register (address x026) followed by writing a ??to the tgcore_rstb register. this will start the inter- nal timing core operation. next, initialize the internal circuitry by first writing ?10101?or ?3?decimal to the initial1 register (address x020). finally, write ?00100?or ??deci- mal to the initial2 register (address x00f). 4. write a ??to the preventupdate register (address x019). this will prevent the updating of the serial register data. 5. write to desired registers to configure high speed timing and horizontal timing. 6. write a ??to the out_cont register (address x016). this will allow the outputs to become active after the next vd/hd rising edge. 7. write a ??to the preventupdate register (address x019). this will allow the serial information to be updated at next vd/hd falling edge. 8. the next vd/hd falling edge allows register updates to occur, including out_cont, which enables all clock outputs. analog front end description and operation the ad9848/ad9849 signal processing chain is shown in fig ure 15. each processing step is essential in achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.5 v to be compatible with the 3 v analog supply signal of the ad9848/ad9849. correlated double sampler the cds circuit samples each ccd pixel twice to extract the video information and reject low frequency noise. the timing shown in figure 6 illustrates how the two internally generated cds clocks, shp and shd, are used to sample the reference level and data level of the ccd signal, respectively. the placement of the shp and shd sampling edges is determined by the setting of the shpposloc and shdposloc registers located at address 0xf0 and 0xf1, respectively. placement of these two clock signals is critical to achieve the best performance from the ccd. input clamp a line-rate input clamping circuit removes the ccd? optical black offset. this offset exists in the ccd? shielded black reference pixels. the ad9848/ad9849 removes this offset in the input stage to minimize the effect of a gain change on the system black level, usually called the ?ain step.?another advantage of remov- ing this offset at the input stage is to maximize system headroom. some area ccds have large black level offset voltages that can significantly reduce the available headroom in the internal circuitry when higher vga gain settings are used, if not corrected after the input stage. horizontal timing examples are shown on the last page of the applications information section. it is recommended that the clpdm pulse be used during valid ccd dark pixels. clpdm may be used during the optical black pixels, either together with clpob or separately. the clpdm pulse should be a minimum of four pixels wide. power-up procedure vdd (input) serial writes vd (output) 1 h odd field even field ... ... digital outputs clocks active when out_cont register is updated at vd/hd edge h1/h3, rg h2/h4 t pwr cli (input) hd (output) 1v ... ... figure 14. recommended power-up sequence
rev. a ad9848/ad9849 ?4 0.1 f 0.1 f 0.1 f 1.0 f 1.0 f 0.1 f 0.1 f 0db to 36db clpdm ccdin digital filter clpob dc restore optical black clamp vga 8-bit dac clamp level register 8 vga gain register 10 cds internal v ref 2v full scale ?db to +10db 10/12 precision timing generation byp1 byp 2 shp shd pxga 1.5v output data latch reft refb dout phase v-h timing generation shp shd dout phase clpdm clpob pblk pblk 1.0v 2.0v dout byp 3 input offset clamp cml avdd 2 internal biasing ad9848/ad9849 10-/12-bit adc figure 15. analog front end block diagram 220 33 1 1 vd notes 1. vd falling edge will reset the pxga gain register steering to ?101?line. 2. hd falling edges will alternate the pxga gain register steering between ?101?and ?323?lines. 3. fld status is ignored. hd 11 0 x x pxga gain register fld 0 odd field even field 0220 33 1 1 11 0 0 0 0 figure 16a. mosaic separate mode
rev. a ad9848/ad9849 ?5 000 11 1 1 vd notes 1. fld falling edge (start of odd field) will reset the pxga gain register steering to ?101?line. 2. fld rising edge (start of even field) will reset the pxga gain register steering to ?323?line. 3. hd falling edges will reset the pxga gain register steering to either ??(fld = odd) or ??(fld = even). hd 11 0 x x pxga gain register fld 0 odd field even field 0222 33 3 3 33 2 2 2 0 figure 16b. mosaic interlaced mode 110 22 1 1 vd notes 1. vd falling edge will reset the pxga gain register steering to ?101?line. 2. hd falling edges will alternate the pxga gain register steering between ?101?and ?212?lines. 3. all fields will have the same pxga gain steering pattern (fld status is ignored). hd 11 0 x x pxga gain register fld 0 odd field even field 0110 22 1 1 11 0 0 0 0 figure 16c. mosaic repeat mode 020 10 0 1 vd notes 1. each line follows ?12012?steering pattern. 2. vd and hd falling edges will reset the pxga gain register steering to ?. 3. fld status is ignored. hd 10 2 x x pxga gain register fld 0 odd field even field 2020 10 0 1 10 2 0 2 0 figure 16d. three-color mode
rev. a ad9848/ad9849 ?6 200 12 0 1 vd notes 1. vd falling edge will reset the pxga gain register steering to ?12012?line. 2. hd falling edges will alternate the pxga gain register steering between ?12012?and ?10210?lines. 3. fld status is ignored. hd 10 2 x x pxga gain register fld 0 odd field even field 2200 12 0 1 10 2 0 2 0 figure 16e. three-color mode ii 020 13 3 1 vd notes 1. each line follows ?1230123?steering pattern. 2. vd and hd falling edges will reset the pxga gain register steering to gain register ?. 3. fld status is ignored. hd 13 2 x x pxga gain register fld 0 odd field even field 2020 13 3 1 13 2 0 2 0 figure 16f. four-color mode 200 31 3 1 vd notes 1. vd falling edge will reset the pxga gain register steering to ?1230123?line. 2. hd falling edges will alternate the pxga gain register steering between ?1230123?and ?3012301?lines. 3. fld status is ignored. hd 13 2 x x pxga gain register fld 0 odd field even field 2200 31 3 1 13 2 0 2 0 figure 16g. four-color mode ii
rev. a ad9848/ad9849 ?7 pxga the pxga provides separate gain adjustment for the individual color pixels. a programmable gain amplifier with four separate values, the pxga has the capability to ?ultiplex?its gain value on a pixel-to-pixel basis (see figure 17). this allows lower output color pixels to be gained up to match higher output color pixels. also, the pxga may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed. the four different gain values are switched according to the ?olor steering?circuitry. seven different color steering modes for different types of ccd color filter arrays are programmed in the ad9848/ad9849 afe register, ctlmode, at a ddress 0x06 (see figures 16a to 16g for timing examples). for example, mosaic separate steering mode accommodates the popular ?ayer arrangement of red, green, and blue filters (see figures 18a and 18b). color steering control 4:1 mux 3 gain0 gain1 gain2 gain3 pxga pxga steering mode selection 2 6 vd hd pxga gain registers control register bits d0?2 shp/shd vga cds figure 17. pxga block diagram rgr rgr gb b gb b rgr rgr gb b gb b gain0, gain1, gain0, gain1... line0 gain2, gain3, gain2, gain3... line1 gain0, gain1, gain0, gain1... line2 ccd: progressive bayer mosaic separate color steering mode figure 18a. ccd color filter example: progressive scan rgr rgr rgr r gr rgr rgr rgr r gr gain0, gain1, gain0, gain1... line0 gain0, gain1, gain0, gain1... line1 gain0, gain1, gain0, gain1... line2 ccd: interlaced bayer even field vd selected color steering mode gb b gb b gb b gb b gb b gb b gb b gb b gain2, gain3, gain2, gain3... line0 gain2, gain3, gain2, gain3... line1 gain2, gain3, gain2, gain3... line2 odd field figure 18b. ccd color filter example: interlaced the same bayer pattern can also be interlaced, and the vd selected mode should be used with this type of ccd (see figure 18b). the color steering performs the proper multiplexing of the r, g, and b gain values (loaded into the pxga gain registers) and is synchronized by the user with vertical (vd) and horizontal (hd) sync pulses. for more detailed information, see the pxga timing section. the pxga gain for each of the four channels is variable from ? db to +10 db, controlled in 64 steps through the serial interface. the pxga gain curve is shown in figure 19. pxga gain register code 10 32 pxga gain ?db 40 48 58 0 8 16 24 31 8 6 4 2 0 ? (011111) (100000) figure 19. pxga gain curve
rev. a ad9848/ad9849 ?8 variable gain amplifier the vga stage provides a gain range of 2 db to 36 db, program- mable w ith 10-bit resolution through the serial digital interface. combined with 4 db from the pxga stage, the total gain range for the ad9848/ad9849 is 6 db to 40 db. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full- scale range of 2 v. when compared to 1 v full-scale systems (such as adi? ad9803), the equivalent gain range is 0 db to 34 db. the vga gain curve is divided into two separate regions. when the vga gain register code is between 0 and 511, the curve follows a (1 + x)/(1 ?x) shape, which is similar to a ?inear-in-db characteristic. from code 512 to code 1023, the curve follows a ?inear-in-db?shape. the exact vga gain can be calculated for any gain register value by using the following two equations: code range gain equation (db) 0?11 gain = 20 log 10 ([658 + code ]/[658 ? code ]) ?0.4 512?023 gain = (0.0354)( code ) ?0.04 vga gain register code 36 0 vga gain ?db 127 255 383 511 639 767 895 1023 30 24 18 12 6 0 figure 20. vga gain curve (gain from pxga not included) optical black clamp the optical black clamp loop removes residual offsets in the signal chain to track low frequency variations in the ccd? black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with a fixed black level reference, selected by the user in the clamp level register. the value can be programmed between 0 lsb and 63.75 lsb on the ad9848 and between 0 lsb and 255 lsb on the ad9849. the clamp level can be programmed with 8-bit resolution. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a d/a converter. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during the post processing, the ad9848/ad9849 optical black clamping may be disabled using bit d2 in the oprmode register. when the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. the clpob pulse should be placed during the ccd? optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide to minimize clamp noise. shorter pulse- widths may be used, but clamp noise may increase, and the ability to track low frequency variations in the black level will be reduced. see the section on horizontal clamping and blanking and also the applications information section for timing examples. a/d converter the ad9848/ad9849 uses high performance 10-bit/12-bit adc architecture, optimized for high speed and low power. differential nonlinearity (dnl) performance is typically better than 0.5 lsb. the adc uses a 2 v input range. better noise performance results from using a larger adc full-scale range. see tpc 1 to tpc 4 for typical linearity and noise performance plots for the ad9848/ad9849. applications information external circuit configuration the ad9848/ad9849 recommended circuit configuration for external mode is shown in figure 21. all signals should be carefully routed on the pcb to maintain low noise performance. the ccd output signal should be connected to pin 29 through a 0.1 f capacitor. the ccd timing signals h1?4 and rg should be routed directly to the ccd with minimum trace lengths, as shown in figures 22a and 22b. the digital outputs and clock inputs are located on pins 1?2 and pins 36?8 and should be connected to the digital asic, away from the analog and ccd clock signals. the cli signal from the asic may be routed under the package to pin 23. this will help separate the cli signal from the h1?4 and rg signal routing. grounding and decoupling recommendations as shown in figure 21, a single ground plane is recommended for the ad9848/ad9849. this ground plane should be as con- tinuous as possible, particularly around pins 25?5. this will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all decoupling capacitors should be located as close as possible to the package pins. plac- ing series resistors close to the digital output pins (pins 1?2, 47?8) may help reduce digital code transition noise. if the digital outputs must drive a load larger than 20 pf, buffering is recommended to minimize additional noise. power supply decoupling is very important for low noise performance. figure 21 shows the local high frequency decoupling capacitors, but additional capacitance is recommended for lower frequencies. additional capacitors and ferrite beads can further reduce noise.
rev. a ad9848/ad9849 ?9 driving the cli input the ad9848/ad9849? master clock input (cli) may be used in two different configurations, depending on the application. figure 23a shows a typical dc-coupled input from the master clock source. when the dc-coupled technique is used, the master clock signal should be at standard 3 v cmos logic levels. as shown in figure 23b, a 1000 pf ac-coupling capacitor may be used between the clock source and the cli input. in this configuration, the cli input will self-bias to the proper dc voltage level of approxi- mately 1.4 v. when the ac-coupled technique is used, the master clock signal can be as low as 500 mv in amplitude. 17 ccd imager signal out 18 13 14 20 29 h2 rg h3 h4 h1 h2 h1 rg ad9848/ad9849 ccdin figure 22a. ccd connections (2 h-clock) 3v digital supply serial interface 3 ccd signal clock inputs 6 0.1 f 36 35 34 33 32 31 30 29 28 27 26 25 3v driver supply 13 14 15 16 clock input 17 18 19 20 21 22 23 24 1 2 rg driver supply 3 h driver supply 4 5 6 7 8 9 10 11 3v analog supply 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) sl reft refb cmlevel 0.1 f avss3 avdd3 byp3 d2 d3 1 f d4 d5 d6 dvss3 1 f dvdd3 d7 d8 d9 d10 ccdin byp2 byp1 avdd2 ad9849 ( msb) d11 avss2 d1 d0 (lsb) 3v analog supply dvdd4 dvss4 hd vd pblk hblk clpdm 0.1 f clpob sck sdi h1 h2 dvss1 dvdd1 h3 h4 dvss2 rg dvdd2 avss1 cli avdd1 3v analog supply data outputs 12 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f high speed clocks 5 figure 21. recommend circuit configuration for external mode
rev. a ad9848/ad9849 ?0 ccd imager signal out 13 14 20 29 rg h3 h4 h2 h1 rg ad9848/ad9849 ccdin h2 h1 17 18 h1 h2 figure 22b. ccd connections (4 h-clock) cli 23 master clock ad9848/ad9849 asic figure 23a. cli connection, dc-coupled cli 23 master cloc k ad9848/ad9849 asic lpf 1nf figure 23b. cli connection, ac-coupled internal mode circuit configuration the ad9848/ad9849 may be used in internal mode using the circuit configuration of figure 24. internal mode uses the same circuit as figure 21, except that the horizontal pulses (clpob, clpdm, pblk, and hblk) are internally generated in the ad9848/ad9849. these pins may be grounded when internal mode is used. only the hd and vd signals are required from the asic. hd/vd inputs 2 44 39 43 42 41 40 hd vd pblk hblk clpdm clpob ad9848/ad9849 figure 24. internal mode circuit configuration timing examples for different sequences 2 4 48 10 v h 28 sequence 3 sequence 2 sequence 2 figure 25. typical ccd
rev. a ad9848/ad9849 ?1 timing examples (continued) vert shift dummy invalid pixels vert shift invalid pixels ccdin shp shd h1/h3 h2/h4 hblk pblk clpob clpdm eff. pixels optical black vert shift dummy vert shift ccdin shp shd h1/h3 h2/h4 hblk pblk clpob clpdm optical black eff. pixels optical black vert shift dummy ccdin shp shd h1/h3 h2/h4 hblk pblk clpob clpdm optical black vert shift effective pixels ob figure 27. sequence 2: vertical optical black figure 26. sequence 1: vertical blanking figure 28. sequence 3: effective pixels
rev. a ?2 ad9848/ad9849 c02498??/03(a) printed in u.s.a. outline dimensions 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane revision history location page 1/03?ata sheet changed from rev. 0 to rev. a. change to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 change to register description table ?hblk # bits 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 changes to recommended power sequence section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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